An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking |
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| Institution: | 1. Department of Electronic Engineering, City University of Hong Kong, Hong Kong SAR;2. Center for Neural Engineering, Department of Biomedical Engineering, University of Southern California, Los Angeles, CA 90089, USA;1. Department of Electrical Engineering and Computer Science, Seoul National University, 151-744 Seoul, Korea;2. Department of Electrical and Computer Engineering, University of Texas at Austin, TX 78712, United States;1. State Key Laboratory of Integrated Service Network, Xidian University, China;2. Institute of Microelectronics, Xidian University, China;3. Key Laboratory of Computer System and Architecture Institute of Computing Technology, Chinese Academy of Sciences, China;4. Science and Technology on Information Transmission and Dissemination in Communication Networks Laboratory, The 54th Institute of CETC, China;1. Department of Mechanical and Aeronautical Engineering, University of Pretoria, Private Bag X20, Hatfield, Pretoria 0028, South Africa;2. Modelling and Digital Science, Council for Scientific and Industrial Research, P.O. Box 395, Pretoria 0001, South Africa;3. Department of Mechanical Engineering, University of Cape Town, Private Bag X3, Rondebosch 7701, South Africa |
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| Abstract: | Recent studies have verified the efficiency of stochastic state point process filter (SSPPF) in coefficients tracking in the modeling of the mammalian nervous system. In this study, a hardware architecture of SSPPF is both designed and implemented on a field-programmable gate array (FPGA). It provides a time-efficient method to investigate the nonlinear neural dynamics through coefficients tracking of a generalized Laguerre–Volterra model describing the spike train transformations of different brain sub-regions. The proposed architecture is able to process matrices and vectors with arbitrary sizes. It is designed to be scalable in parallel degree and to provide different customizable levels of parallelism, by exploring the intrinsic parallelism of the FPGA. Multiple architectures with different degrees of parallelism are explored. This design maintains numerical precision and the proposed parallel architectures for coefficients estimation are also much more power efficient. |
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| Keywords: | SSPPF Adaptive filter Neural modeling Field-programmable gate array |
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