| 一种宽带数字化雷达正交解调接收机的设计与实现 |
| |
| 引用本文： | 邱兆坤,马云,王伟,陈曾平.一种宽带数字化雷达正交解调接收机的设计与实现[J].信号处理,2005,21(4):350-354. |
| |
| 作者姓名： | 邱兆坤 马云 王伟 陈曾平 |
| |
| 作者单位： | 长沙国防科技大学电子科学与工程学院ATR实验室,长沙,410073 |
| |
| 基金项目： | 国家863基金资助项目(2002AA731130) |
| |
| 摘 要： | 描述了一种高效的雷达宽带正交接收机的全数字设计方法,给出了设计条件。并基于FPGA采用此方法实现了八路雷达信号实时正交解调接收的设计。最后对系统性能进行了测试,并与软件解调结果进行了对比,验证了设计的正确性。
|
| 关 键 词： | 正交解调 数字下变频 多项滤波 FPGA CPCI总线 |
| 修稿时间： | 2003年12月16 |
Design and Implementation of an Wideband Digitized Radar Quadrature Demodulation Receiver |
| |
| Qiu Zhaokun,Ma Yun,Wang Wei,Chen Zengping.Design and Implementation of an Wideband Digitized Radar Quadrature Demodulation Receiver[J].Signal Processing,2005,21(4):350-354. |
| |
| Authors: | Qiu Zhaokun Ma Yun Wang Wei Chen Zengping |
| |
| Abstract: | A method to design efficient radar wideband digital quadrature demodulation receiver is described. The design condition is also given. Then an efficient 8-channel real-time radar signal quadrature demodulation receiver with this method is implemented based on FPGA. Finally, the performance of the receiver is tested. By comparing to the result of software demodulation, it shows the validity of the design. |
| |
| Keywords: | quadrature demodulation digital downconversion polyphase filtering FPGA CPCI bus |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
