| Efficient and Low-Latency Systolic Array Architecture for Full Searches in Block-Matching Motion Estimation |
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| 引用本文： | 张武健,邱晓海,周润德,陈弘毅. Efficient and Low-Latency Systolic Array Architecture for Full Searches in Block-Matching Motion Estimation[J]. 清华大学学报, 2001, 0(4) |
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| 作者姓名： | 张武健 邱晓海 周润德 陈弘毅 |
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| 作者单位： | ZHANG Wujian，QIU Xiaohai，ZHOU Runde，CHEN Hongyi Kondo Toshio ，Nakashima Takayoshi ，Ishitani Tsunehachi Institute of Microelectronics，Tsinghua University，Beijing 100084，China; NTT Electronics Corporation，Ebina 243 0432，Japan |
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| 摘 要： | IntroductionEmerging applications such as interactive videocommunication,digital broadcasting,and digitalstorage media require video compression.Thecomputational complexity requires hardware forreal time processing.A central component of video compression isthe motion estimation unit,which exploits thetemporal redundancy of a video sequence.Block-matching,the most popular motion estimationmethod,searches for a motion vector thatminimizes the distortion error between amacroblock of a frame to b…
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Efficient and Low-Latency Systolic Array Architecture for Full Searches in Block-Matching Motion Estimation |
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| Abstract: | |
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| Keywords: | motion estimation full search systolic array low latency low power |
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