基于低功耗双边沿D触发器的任意进制异步计数器设计

从D触发器激励表入手，分别给出了采用单边沿D触发器和双边沿D触发器的2^n进制异步加法计数器、减法计数器的设计方法．在此基础上，采用逻辑函数修改技术，通过实例讨论了基于单边沿D触发器和双边沿D触发器的异步任意进制计数器的设计．该设计方法方便，快速，具有一定的实用意义．

Design of module-N asynchronous counter consisting of low power double-edge-triggered D flip-flop

Starting from the excitation table for the D flip-flop, the logic design of module-2^n asynchronous up/down counter consisting of single-edge-triggered D flip-flop or double-edge-triggered D flip-flop is introduced. Based on it, some questions about how to use logic function modification techniques to achieve module-N asynchronous counter are also analyzed. The design examples show that spreading this design method to any module-N up/down counter has the advantages of being easily used and quickly designed, and is of certain practical significance. Furthermore, the application of double-edge-triggered D flip-flop, comparing with single-edge-triggered D flip-flop, the frequency of clock can be reduced to half, so power of the circuit can be reduced availably.