复杂SOC的软硬件协同验证解决方案

为了提高产品的验证覆盖率和产品的首次成功率,验证工程师越来越多的使用固件、硬件诊断程序和其它软件部分作为实际嵌入式处理器的SoC验证的激励,以保证RTL设计与最终设计实现的的应用环境相同,并覆盖更为复杂的场景,但该RTL验证环境对软件调试的可视性比较有限。Mentor公司的Questa Codelink提供了独特的软硬件协同验证的技术可以让验证人员同时看到软件的执行情况和与软件同步的硬件波形,其回放模式减少了仿真等待的时间,可以快速追踪并定位到程序出错的地方。Codelink也提供了多核调试的技术,可同时看到软件在不同处理器的执行情况,极大地提高了多核验证的效率。

HW/SW Coverification Solution for Complex SoC Design

In order to improve function coverage and first silicon success, more and more firmware, hardware diagnostics, and other software as a basis for creating functional verification tests are used by verification engineers to make the design run in the similar environment after design is taped out. It can cover more complex scenarios, but it lacks of the visibility to debug hardware and software at the same time. Mentor Graphic’s Questa Codelink provided unique HW SW co-verification technique to let verification engineers monitor the execution status of SW and the synchronized HW waveform to reduce online simulation time and locate the issues of SW quickly. Also Codelink provided the technique to debug multiple processors in parallel, which can improve verification efficiency greatly.