基于门冻结技术的无冒险RS触发器设计

数字电路中的冒险现象不仅会导致电路的误操作，而且消耗了很多能量、增加了操作时间，因此在电路设计中冒险的检测和消除非常重要．文章介绍了门冻结技术的基本思想，以此为基础给出了基于F门的CMOS与非门、或非门的逻辑单元电路设计，并将其应用到RS触发器的设计中，经PSPICE模拟显示，与传统的同步RS触发器相比，所设计的基于F门的同步RS触发器电路不仅具有正确的逻辑功能，消除了冒险，而且使电路的功耗也得到了有效地降低。

Design of hazard-free RS flip-flop based on gate freezing

Hazards in digital circuits may not only cause errors in the circuit operation, but also consume a lot of power, and add to the computation time. Therefore it is very important to detect and eliminate hazards in circuit designs. By introducing the basic idea of gate freezing, the designs of the CMOS NAND,NOR logic cells based on F Gates were presented, and then a new kind of RS flip flop was proposed. By the PSPICE simulation, compared with the tranditional synchronous RS flip flop, the designed synchronous RS flip-flop based on F gate not only has correct logic functions, but also eliminates hazards, and reduces the power dissipation.