| 基于低功耗双边沿JK触发器的异步时序电路设计 |
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| 引用本文： | 赵敏笑,余红娟,陈偕雄. 基于低功耗双边沿JK触发器的异步时序电路设计[J]. 浙江大学学报(理学版), 2005, 32(1): 45-48 |
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| 作者姓名： | 赵敏笑 余红娟 陈偕雄 |
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| 作者单位： | 1. 浙江大学,信息与电子工程系,浙江,杭州,310028;金华职业技术学院,浙江,金华,321017
2. 浙江大学,信息与电子工程系,浙江,杭州,310028 |
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| 摘 要： | 从JK触发器的激励表出发,介绍了基于单边沿JK触发器的同步时序电路和异步时序电路设计,提出了双边沿JK触发器的完整状态方程,并以此为基础讨论了基于双边沿JK触发器的异步时序电路的设计方法.
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| 关 键 词： | 低功耗 双边沿触发器 异步时序电路 逻辑设计 |
| 文章编号： | 1008-9497(2005)01-045-04 |
| 修稿时间： | 2004-04-06 |
Logic design of asynchronous sequence circuit based on low power double-edge-triggered JK flip-flop |
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| ZHAO Min-xiao. Logic design of asynchronous sequence circuit based on low power double-edge-triggered JK flip-flop[J]. Journal of Zhejiang University(Sciences Edition), 2005, 32(1): 45-48 |
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| Authors: | ZHAO Min-xiao |
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| Affiliation: | ZHAO Min-xiao~ |
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| Abstract: | Starting from the excitation table for the JK Flip-flop, this paper introduces the logic design of synchronous sequential circuit and asynchronous sequential circuit based on single-edge-triggered JK flip-flop, and proposes the complete state equation. Besides, it discusses the logic design of asynchronous sequential circuit based on double-edge-triggered JK flip-flop by means of state-transformation K-map, gives out several practical design examples to show the design method and the general design formulas for both synchronous and asynchronous n-bit binary counters. The design examples show that the design methods presented here are effective. |
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| Keywords: | low power double-edge-triggered flip-flop asynchronous sequential circuit logic design |
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