A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures |
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Authors: | Ma Fei Liu Hong-Xia Kuang Qian-Wei Fan Ji-Bin |
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Institution: | Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Material and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China |
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Abstract: | We investigate the influence of voltage drop across the lightly doped drain (LDD) region and the built-in potential on MOSFETs, and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers. The model can predict the fringing-induced barrier lowering effect and the short channel effect. It is also valid for non-LDD MOSFETs. Based on this model, the relationship between threshold voltage roll-off and three parameters, channel length, drain voltage and gate dielectric permittivity, is investigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends slightly on channel length, drain voltage, and gate dielectric permittivity. The model is verified at the end of the paper. |
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Keywords: | threshold voltage high-k gate dielectric fringing-induced barrier lowering short channel effect |
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