A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through (LPT) carrier stored trench bipolar transistor (CSTBT) with buried p-layer (BP) is proposed in this paper. Since the negative charges in the BP layer modulate the bulk electric field distribution, the electric field peaks both at the junction of the p base/n-type carrier stored (N-CS) layer and the corners of the trench gates are reduced, and new electric field peaks appear at the junction of the BP layer/N^- drift region. As a result, the overall electric field in the N^- drift region is enhanced and the proposed structure improves the breakdown voltage (BV) significantly compared with the LPT CSTBT. Furthermore, the proposed structure breaks the limitation of the doping concentration of the N-CS layer (N_{N -CS}) to the BV, and hence a higher N_N-CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop (V_ce(sat)) can be obtained with almost constant BV. The results show that with a BP layer doping concentration of N_BP=7 × 10¹⁵ cm^-3, a thickness of L_BP=2.5 μm, and a width of W_BP=5 μm, the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V, with N_N-CS increasing from 5 × 10¹⁵ cm^-3 to 2.5 × 10¹⁶ cm^-3. However, with the same N^--drift region thickness of 150 μm and N_N-CS, the BV of the CSTBT decreases from 1598 V to 247 V. Meanwhile, the V_ce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with N_N-CS increasing from 5 × 10¹⁵ cm^-3 to 2.5 × 10¹⁶ cm^-3.