一种兼顾速度和功率损耗的硅探测器模拟前端电路设计

提出了一种兼顾速度和功率损耗的增益可调模拟前端电路，适用于硅探测器。该电路主要由快速电荷灵敏放大器、整形器以及可调节主要参数的控制系统组成。其中快速电荷灵敏放大器由低噪音场效晶体管（JFET）和电流反馈运算放大器构成，以确保较高频率和较短上升时间。整形器为五阶复数滤波器，能够提供较高的对称脉冲。通过实验验证了其可行性，在电容小于100 pF的范围内，实现了6种可调增益且兼顾了速度和功率损耗，电荷灵敏放大器上升时间为12ns，功率损耗为96mW。当探测器电容为40 pF时，等效噪音电荷（ENC）均值为180e-。

Design of analog front end circuit for silicon detector with both speed and power loss

A gain adjustable analog front end circuit considering both speed and power loss is proposed, which is suitable for silicon detector. The circuit is mainly composed of a fast charge sensitive amplifier, shaper and adjust the main parameters of control system, adjust the output signal of detector charge. The fast charge sensitive amplifier consists of a low noise field effect transistor (JFET) and a current feedback operational amplifier to ensure a high frequency and short rise time. The shaping device is a five - order complex filter, which can provide high symmetrical pulse. Through the experiment verified the feasibility, in the capacitance of the detector is less than 100 pf range and realize the six adjustable gain and the balance between the speed and power loss, charge sensitive amplifier rise time 12ns, power loss 96mW. When the detector capacitance is 40 pF, the equivalent noise charge (ENC) means is 180e-.