| 双边沿移位寄存器的设计原理及其应用 |
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| 引用本文： | 朱挺,吴训威. 双边沿移位寄存器的设计原理及其应用[J]. 浙江大学学报(理学版), 2004, 31(1): 29-33,42 |
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| 作者姓名： | 朱挺 吴训威 |
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| 作者单位： | 1. 浙江大学,信息与电子工程学系,浙江,杭州,310027
2. 宁波大学,电路与系统研究所,浙江,宁波,315211 |
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| 摘 要： | 从消除时钟信号冗余跳变而致的无效功耗的要求出发,提出双边沿移位寄存器的设计思想.该移位寄存器的功能已用PSPICE程序模拟验证.使用该移位寄存器设计双边沿移位计数器的实例被演示.对模拟所得数据的计算结果表明,与实现相同功能的单边沿移位寄存器相比,由于工作频率减半,双边沿移位寄存器的功耗有明显降低
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| 关 键 词： | 低功耗 移位寄存器 逻辑设计 集成电路 |
| 文章编号： | 1008-9497(2004)01-029-05 |
Design principle and application of double-edge-triggered shift register |
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| ZHU Ting,WU Xun-wei. Design principle and application of double-edge-triggered shift register[J]. Journal of Zhejiang University(Sciences Edition), 2004, 31(1): 29-33,42 |
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| Authors: | ZHU Ting WU Xun-wei |
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| Affiliation: | ZHU Ting~1,WU Xun-wei~2 |
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| Abstract: | To eliminate the bootless power dissipation of the redundant transition of the clock, a design method named DET(double-edge-triggered) shift register is proposed. The logic function of this DET shift register is proved by PSPICE simulation. A DET shift counter designed with the DET shift register is demonstrated. Calculation for the data from simulation shows that power dissipation of DET shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart SET shift register. |
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| Keywords: | low power shift register logic design integrated circuits |
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