Digital implementation of the preloaded filter pulse processor |
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Authors: | G P Westphal G R Cadek N Kerö Th Sauter P C Thorwartl |
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Institution: | (1) Atominstitut der Österreichischen Universitäten, Schüttelstraße 115, A-1020 Vienna, Austria;(2) Institut für Allgemeine Elektrotechnik und Elektronik, CAD Division, Technical University of Vienna, Gußhausstraße 27-29, A-1040 Vienna, Austria |
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Abstract: | Adapting it's processing time to the respective pulse intervals, the Preloaded Filter (PLF_ pulse processor offers optimum resolution together with highest possible throughput rates. The PLF algorithm could be formulated in a recursive manner which made possible it's implementation by means of a large field-programmable gate array, as a fast, pipe-lined digital processor with 10 MHz maximum throughput rate. While pre-filter digitization by an ADC with 12 bit resolution and 10 MHz sampling rate resulted in a poorer resolution than that of an analog filter, a digital PLF based on an ADC with 14 bit resolution and 10 MHz sampling rate, surpassed high-quality analog filters in resolution, throughput rate and long-term stability. |
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