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On-Chip SRAM内建自测试及其算法的研究
引用本文:刘有耀,李彬.On-Chip SRAM内建自测试及其算法的研究[J].数字通信,2014(4):14-18.
作者姓名:刘有耀  李彬
作者单位:西安邮电大学,西安710061;西安邮电大学,西安710061
基金项目:国家自然科学基金(61136002,61272120)
摘    要:具体研究on-Chip SRAM的内建自测试及其算法.在引入嵌入式存储器内建自测试的基础上,详细分析on-Chip SRAM内建自测试的具体实现方法,反映出内建自测试对于简化测试程序和缩短测试时间,从而降低测试成本的重要性.详细描述在测试on-Chip SRAM时常用的算法,并具体分析非传统性测试算法——Hammer算法和Retention算法.

关 键 词:片上静态随机存储器  内建自测试  故障模型  测试算法
修稿时间:5/4/2014 12:00:00 AM

Research on built-in self-test and test algorithm of on-Chip SRAM
LIU Youyao and LI Bin.Research on built-in self-test and test algorithm of on-Chip SRAM[J].Digital Communication,2014(4):14-18.
Authors:LIU Youyao and LI Bin
Institution:(xi' an University of Posts and Telecommunications, Xi' an 710061, P. R. China)
Abstract:This paper mainly talked about the MBIST (memory built-in self-test) and the test algorithm of on-Chip SRAM. Based on the embedded memory BIST (built-in self-test), it detailed analyzed the concrete implementation method of the SRAM BIST, which shows the importance of MBIST to memory test. MBIST can not only simplify the whole test program, but also reduce the test time and test cost. It also focus on the test algorithm especially Non-Traditional algorithm-- Hammer test and Retention test.
Keywords:on-Chip SRAM  BIST  fault model  test algorithm
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