| 双速自适应以太网MAC设计及FPGA验证 |
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| 引用本文： | 曹云鹏,钱敏,杨翠军.双速自适应以太网MAC设计及FPGA验证[J].通信技术,2010,43(11):87-89,92. |
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| 作者姓名： | 曹云鹏 钱敏 杨翠军 |
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| 作者单位： | 苏州大学电子信息学院微电子系,江苏苏州215006 |
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| 摘 要： | 嵌入式以太网有着广泛的应用,是目前嵌入式系统研究的一个重要领域。设计了嵌入式以太网的媒体访问控制器（MAC）。简单介绍了以太网MAC子层协议;用Verilog-HDL设计了10/100Mb/s自适应以太网控制器,其中包括片上总线总线口、发送模块、接收模块和流量控制模块等几部分;建立了相关测试向量,在ModelSimPLUS6.4SE软件中进行了仿真和调试,并成功用ALTERA的FPGA进行了验证;逻辑仿真和物理板级验证结果都表明该设计实现了10/100Mb/s以太网通信的相关功能。
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| 关 键 词： | 以太网控制器 MAC Verilog HDL 验证 |
Design and FPGA Verification of Dual-speed Adaptive Ethernet MAC |
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| CAO Yun-peng,QIAN Min,YANG Cui-jun.Design and FPGA Verification of Dual-speed Adaptive Ethernet MAC[J].Communications Technology,2010,43(11):87-89,92. |
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| Authors: | CAO Yun-peng QIAN Min YANG Cui-jun |
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| Institution: | (Microelectronics Department,Suzhou University,Suzhou Jiangsu 215006,China) |
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| Abstract: | The embedded ethernet is widely applied,and is an important field for research of embedded system.The MAC controller for embedded ethernet is designed.The MAC sublayer protocol of ethernet and the architecture of ethernet data frame are briefly described.The 10/100Mb/s adaptive ethernet controller is designed with VerilogHDL,including WISHBONE bus interface,Tx/Rx modules,flow control module,etc.The related testing vectors are established,and the whole design is simulated with ModelSim PLUS 6.4SE tools and successfully verified by ALTERA FPGA.The logic simulation and the FPGA physical board-level verification indicate that the related functions of the 10/100Mb/s adaptive Ethernet controller are successfully realized. |
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| Keywords: | ethernet controller MAC Verilog HDL verification |
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