Single event transient pulse width measurement of 65-nm bulk CMOS circuits |
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| Authors: | Yue Suge Zhang Xiaolin and Zhao Xinyuan |
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| Institution: | 1. Beijing University of Aeronautics & Astronautics, Beijing 100191, China ;Beijing Microelectronics Technology Institute, Beijing 100076, China;2. Beijing University of Aeronautics & Astronautics, Beijing 100191, China;3. Beijing Microelectronics Technology Institute, Beijing 100076, China |
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| Abstract: | Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed. |
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| Keywords: | SET pulsewidth 65 nm |
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