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A Self-Calibrated Pipeline ADC with 200 MHz IF-Sampling Frontend |
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| Authors: | Mikko Waltari Lauri Sumanen Tuomas Korhonen Kari A I Halonen |
| Institution: | (1) Electronic Circuit Design Laboratory, Helsinki University of Technology, P.O. Box 3000, FIN-02015 HUT, Finland |
| Abstract: | A 13-bit, 50-MS/s pipeline ADC with IF-sampling capability is presented. A high sampling linearity is obtained through the use of bootstrapped switches. A digital self-calibration algorithm with modified capacitor measurement scheme is employed to improve the accuracy of the first two pipeline stages. The prototype, implemented with a 0.35- m BiCMOS (SiGe) technology, shows a 76.5-dB SFDR at a 194.2-MHz signal frequency and dissipates 715 mW power from a 2.9-V supply. |
| Keywords: | analog-to-digital conversion BiCMOS analog intergrated circuits bootstrapped switches delay-locked loop IF sampling jitter operational amplifiers pipeline processing sample-and-hold circuits self-calibration |
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