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基于改进陷阱模型的新型p型隔离层结合场板结构的4H-SiC MESFET的特性研究与优化
引用本文:宋坤,柴常春,杨银堂,贾护军,张现军,陈斌.基于改进陷阱模型的新型p型隔离层结合场板结构的4H-SiC MESFET的特性研究与优化[J].半导体学报,2011,32(7):074003-6.
作者姓名:宋坤  柴常春  杨银堂  贾护军  张现军  陈斌
作者单位:西安电子科技大学,西安电子科技大学,西安电子科技大学,西安电子科技大学
基金项目:国家部委预研项目(51308030201)
摘    要:本文提出了一种致力于抑制表面陷阱影响的新型结构。基于能准确表征4H-SiC材料特性的物理模型和经过实验证明能较好表征表面陷阱作用机理的模型,对器件的特性进行了研究。通过与实际器件制作中主流采用的埋栅-场板结构的4H-SiC MESFET以及实验测试的器件特性的对比,本文提出的结构在整体上对器件的特性有所提高 。新结构引入的 p型隔离层能有效地抑制表面陷阱的影响并且能减小器件在大电压微波应用条件下的栅漏电容;P型隔离层结合场板结构改善了栅极边缘的电场分布,同时能减小单一使用场板结构时场板对沟道引入的附加栅漏电容; 作为微波晶体管,由于更好的抑制了表面陷阱,基于本文提出的结构的4H-SiC MESFET比埋栅-场板结构的器件具有更高的栅延迟抑制比;在实现大功率应用方面,新型结构同样能提供更高的耐压。新结构的4H-SiC MESFET的最大饱和漏电流密度为460mA/mm,在漏电压20V的栅延迟抑制比接近90%。交流特性的分析结果表明,本文提出的结构比埋栅-场板结构的器件的特征频率和最高振荡频率分别高出5%和17.8%。此外,新结构的器件能承受较高的击穿电压,进而保证了器件的大功率密度。针对本文提出的结构进行了优化,以使器件能发挥最好的微波特性并对器件的设计提供一定参考。

关 键 词:MESFET  场板结构  陷阱效应  物理模型  间隔层  碳化硅  优化  基础
修稿时间:3/1/2011 5:16:39 PM

Characteristics and optimization of 4H-SiC MESFET with a novel p-type spacer layer incorporated with a field-plate structure based on improved trap models
Song Kun,Chai Changchun,Yang Yintang,Jia Hujun,Zhang Xianjun and Chen Bin.Characteristics and optimization of 4H-SiC MESFET with a novel p-type spacer layer incorporated with a field-plate structure based on improved trap models[J].Chinese Journal of Semiconductors,2011,32(7):074003-6.
Authors:Song Kun  Chai Changchun  Yang Yintang  Jia Hujun  Zhang Xianjun and Chen Bin
Institution:Xidian University,Xidian University,Xidian University,Xidian University
Abstract:A novel structure of 4H-SiC MESFETs is proposed which focuses on surface trap suppression. Investigation has been made on the characteristics based on physical models for material properties and improved trap models which are proven to have good agreements with experimental data. Compared with characteristics of former fabrication utilized structure with corresponding measured data, proposed structure is shown to improve device properties in comprehensive aspects. A p-type spacer layer introduced in proposed structure is shown to suppress surface trap effect and reduce gate-drain capacitance under large drain voltage in microwave operation. P-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while spacer layer induces less gate-drain capacitance than the well recognized buried gate incorporated with field-plate (BG-FP) structure. For microwave applications, 4H-SiC MESFET for proposed structure has larger gate-lag ratio in saturation region due to better surface trap isolation from conductive channel. For high power applications, proposed structure allows higher operating voltage as well. The maximum saturation current density of 460mA/mm is yielded. Also, the gate-lag ratio under drain voltage of 20V is close to 90%. In addition, a 5% and a 17.8% improvement in fT and fmax are obtained compared with BG-FP MESFET in AC simulation, respectively. Parameters and dimensions of proposed structure are optimized to make the best of device for microwave applications and provide reference for device design.
Keywords:4H-SiC  MESFET  surface trap  p-type spacer layer  microwave application
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