An automated high-level topology generation procedure for continuous-time ΣΔ modulator |
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Authors: | Soumya Pandit [Author Vitae] Chittaranjan Mandal [Author Vitae] [Author Vitae] |
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Institution: | a Institute of Radio Physics and Electronics, Kolkata, India b Indian Institute of Technology, Kharagpur, India |
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Abstract: | This paper presents an automated procedure for generation of high-level topologies for continuous-time ΣΔ modulator system. A functional topology of the system is generated from the given transfer function model of the modulator. Mathematical transformation technique is applied iteratively over the initial topology to generate a functional topology which is optimized for modulator sensitivity, hardware complexity and relative power consumption. This is then implemented using behavioral models of operational transconductance amplifiers and capacitors. The generated high-level topology is ensured to work with reasonable accuracy under non-ideal conditions. The entire procedure has been implemented in Matlab/Simulink environment. Numerical results have been provided to demonstrate the procedure. |
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Keywords: | Analog design automation Analog high-level design Topology generation Sigma delta modulator |
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