数字集成电路故障测试策略和技术的研究进展

IC制造工艺的发展，持续增加着VLSI电路的集成密度，亦日益加大了电路故障测试的复杂性和困难度。作者在承担相应研究课题的基础上，综述了常规通用测试方法和技术，并分析了其局限性。详细叙述了边界扫描测试(BST)标准、可测性设计(DFT)思想和内建自测试(BIST)策略。针对片上系统(SoC)和深亚微米(VDSM)技术给故障测试带来的新挑战，本文进行了初步的论述和探讨。

Research Progress on Strategy and Techniques of Fault Testing on Digital Integrated Circuits

As the density of VLSI circuits increases and the technique of IC manufacturing develops, fault testing on digital integrated circuits becomes more and more complex and difficult to implement. On the basis of the ongoing research work, conventional test methods and techniques are reviewed. Their limitation is analyzed comprehensively. Several testing strategies, such as standards of Boundary Scan Test (BST), principles of Design For Testability (DFT) and Built-In Self-Test (BIST) strategy are described in detail. New difficulties challenging the fault testing on System-on-a-Chip and Very Deep Sub-Micron (VDSM) technology are foreseen and discussed in this review.