Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths |
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Authors: | Sotiris George Kiamal |
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Institution: | aSchool of Electrical and Computer Engineering, National Technical University of Athens, Iroon Polytexneiou 9, GR 15780 Athens, Greece |
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Abstract: | This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an area-time-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a transformation, called uniformity transformation, imposed on the basic architectures of CS-multipliers and CS-chain-adders/subtractors. Experimental results including quantitative and qualitative comparisons with existing reconfigurable arithmetic cores and exploration results of the proposed reconfigurable architecture are provided. |
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Keywords: | Coarse-grain reconfigurable architectures Flexibility inlining Canonical interconnection Carry-save arithmetic Chain addition Array multiplier |
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