| 一种降低高速三维互连芯片层间信号反射的方法 |
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| 引用本文： | 刘晓贤,朱樟明,杨银堂,王凤娟,丁瑞雪,梁华国,徐辉,黄正峰,易茂祥.一种降低高速三维互连芯片层间信号反射的方法[J].半导体学报,2014,35(1):015008-8. |
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| 作者姓名： | 刘晓贤 朱樟明 杨银堂 王凤娟 丁瑞雪 梁华国 徐辉 黄正峰 易茂祥 |
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| 摘 要： | In high speed three-dimensional integrated circuits （3D ICs）, through silicon via （TSV） insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.
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| 关 键 词： | 三维集成电路 信号反射 阻抗匹配 集成芯片 互连结构 多级 调谐频率 SV通道 |
| 收稿时间： | 6/1/2013 12:00:00 AM |
| 修稿时间： | 7/2/2013 12:00:00 AM |
Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips |
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| Liu Xiaoxian,Zhu Zhangming,Yang Yintang,Wang Fengjuan,Ding Ruixue,Liang Huaguo,Xu Hui,Huang Zhengfeng and Yi Maoxiang.Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips[J].Chinese Journal of Semiconductors,2014,35(1):015008-8. |
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| Authors: | Liu Xiaoxian Zhu Zhangming Yang Yintang Wang Fengjuan Ding Ruixue Liang Huaguo Xu Hui Huang Zhengfeng and Yi Maoxiang |
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| Institution: | School of Microelectronics, Xidian University, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi'an 710071, China;School of Microelectronics, Xidian University, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi'an 710071, China;School of Microelectronics, Xidian University, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi'an 710071, China;School of Microelectronics, Xidian University, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi'an 710071, China;School of Microelectronics, Xidian University, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi'an 710071, China;School of Electronic Science and Applied Physics, Heifei University of Technology, Hefei 230009, China;School of Computer and Information, Heifei University of Technology, Hefei 230009, China;School of Computer Science and Engineering, Anhui University of Science and Technology, Huainan 232001, China;School of Electronic Science and Applied Physics, Heifei University of Technology, Hefei 230009, China;School of Electronic Science and Applied Physics, Heifei University of Technology, Hefei 230009, China |
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| Abstract: | In high speed three-dimensional integrated circuits (3D ICs), through silicon via (TSV) insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals. |
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| Keywords: | 3D integration TSV signal reflection impedance matching S-parameter |
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