| 基于异或门自选通的低功耗时钟树综合方案 |
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| 引用本文： | 黄雪晴,于忠臣.基于异或门自选通的低功耗时钟树综合方案[J].中国集成电路,2014(8):12-15. |
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| 作者姓名： | 黄雪晴 于忠臣 |
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| 作者单位： | 北京工业大学北京市嵌入式系统重点实验室,北京 100124 |
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| 摘 要： | 本文介绍一种降低时钟网络功耗的方法。该方法基于电路中寄存器本身的状态值,在采用异或门进行自选通后构建时钟树结构,从而减少时钟信号额外翻转,降低芯片功耗。将该方法应用于一款基于SMIC0.18μmEflash 2p4m工艺下的非接触式智能卡芯片的物理设计。仿真结果表明,与传统时钟树综合方法相比,芯片功耗降低了10.7%。
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| 关 键 词： | 集成电路 异或门自选通 时钟树综合 低功耗 |
Low Power Clock Tree Synthesis Depending on XOR Self-gating |
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| HUANG Xue-qing,YU Zhong-chen.Low Power Clock Tree Synthesis Depending on XOR Self-gating[J].China Integrated Circuit,2014(8):12-15. |
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| Authors: | HUANG Xue-qing YU Zhong-chen |
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| Institution: | (Beijing Embedded System Key Lab, Beijing University of Technology, Beijing 100124, China) |
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| Abstract: | The paper value of flip-flops in signal＇ introduces a method to decrease the power consumption of clock network. It is based on the state the circuit and uses XOR self-gating to build the clock tree for the purpose of decreasing clock s extra smitching and circuit＇ s power consumption. This method is applied to a contactless smart card chip based on SMIC 0.18 μmEflash2p4m process. The simulation result indicates that the chip＇ s power consumption has reduced 10.7% comparing to the traditional clock tree synthesis. |
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| Keywords: | Integrated Circuit （ IC ） XOR self-gating Clock tree synthesis Low power |
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