Investigations on the effect of InSb and InAsSb step-graded buffer layers in InAs0.5Sb0.5 epilayers grown on GaAs (0 0 1)

We report the structural and electrical properties of InAsSb epilayers grown on GaAs (0 0 1) substrates with mid-alloy composition of 0.5. InSb buffer layer and InAs_xSb_1−x step-graded (SG) buffer layer have been used to relax lattice mismatch between the epilayer and substrate. A decrease in the full-width at half-maximum (FWHM) of the epilayer is observed with increasing the thickness of the InSb buffer layer. The surface morphology of the epilayer is found to change from 3D island growth to 2D growth and the electron mobility of the sample is increased from 5.2×10³ to 1.1×10⁴ cm²/V s by increasing the thickness of the SG layers. These results suggest that high crystalline quality and electron mobility of the InAs_0.5Sb_0.5 alloy can be achieved by the growth of thick SG InAsSb buffer layer accompanied with a thick InSb buffer layer. We have confirmed the improvement in the structural and electrical properties of the InAs_0.5Sb_0.5 epilayer by quantitative analysis of the epilayer having a 2.09 μm thick InSb buffer layer and 0.6 μm thickness of each SG layers.