一种带二进制校正的10位100 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种带二进制校正的10位100 MS/s逐次逼近型模数转换器(SAR ADC),主要由自举开关、低噪声动态比较器、电容型数模转换器(C-DAC)、异步SAR逻辑以及数字纠错电路组成。电容型数模转换器采用带2位补偿电容的拆分单调电容转换方案,通过增加2位补偿电容,克服了电容型数模转换器在短时间内建立不稳定和动态比较器失调电压大的问题,使SAR ADC的性能更加稳定。数字纠错电路将每次转换输出的12位冗余码转换成10位的二进制码。使用Spectre进行前仿真验证,使用Virtuoso进行版图设计,后仿真结果表明,当电源电压为1.2 V、采样率为100 MS/s、输入信号为49.903 MHz时,该ADC的SNDR达到58.1 dB,而功耗仅为1.3 mW。

A 10 Bit 100 MS/s SAR ADC with Binary-Scaled Error Compensation

Based on SMIC 65 nm CMOS process, a 10-bit 100 MS/s successive-approximation register (SAR) ADC with 2-bit compensative capacitors was proposed. The ADC mainly consisted of bootstrapped switch, low-noise dynamic comparator, capacitive DAC(C-DAC), asynchronous SAR logic and digital error correction circuit. Splitting monotonic switching method with 2-bit compensative capacitors which made the ADC perform much stably, was adopted to tolerate the settling error of DAC and the offset voltage of dynamic comparator. The digital error correction logic converted the 12 bit redundant codes to 10 bit binary codes. The post-layout simulation showed that the ADC achieved a SNDR of 58.1 dB at 1.2 V power supply and 100 MS/s sampling frequency when the input signal frequency was 49.903 MHz. It consumed only 1.3 mW.