基于FPGA的DES加密算法的高性能实现

在分析DES算法原理的基础上，详细阐述一种基于VHDL描述、FPGA实现的DES加密算法系统的设计和仿真结果。该系统采用了一种基于子密钥预先计算的新型流水线设计方案，克服了传统DES流水线实现方式的缺点，使系统的密钥可动态刷新，并在硬件资源消耗有所降低的情况下，进一步提高系统的处理速度，系统最高时钟频率为222.77MHz，信息加密的速度为14.26Gb／s，是最快软件实现方式的112倍。同时系统还具有设计灵活，可靠性高，可重用性强，升级方便等特点。

High-performance implementation of DES algorithm based on FPGA

First, the DES algorithm principle is introduced. Second, it＇s FPGA implementation based on VHDL is described. Finally the simulation results is presented.In order to improve the traditional DES pipelining design,a novel pipelining method based on sub-key pre-calculated is utilized in this FPGA implementation design. The advantages of the DES system is that the key can be dynamically refreshed,hardware resource consumption is reduced,data processing speed is more improved,the highest clock frequency is up to 222.77MHz,the data rate is up to 14.26Gb/s and is factor 112 times faster than software implementations. Furthermore, the system is a flexible, reliable, reusable, scalable design.