| A novel 10-nm physical gate length double-gate junction field effect transisto |
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| 作者姓名： | 侯晓宇 黄 如 陈 刚 刘 晟 张 兴 俞 滨 王阳元 |
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| 作者单位： | Institute of Microelectronics, Peking University, Beijing 100871, China;Institute of Microelectronics, Peking University, Beijing 100871, China;Institute of Microelectronics, Peking University, Beijing 100871, China;Institute of Microelectronics, Peking University, Beijing 100871, China;Institute of Microelectronics, Peking University, Beijing 100871, China;NASA Ames Research Center, Moffett Field, CA 94035,USA;Institute of Microelectronics, Peking University, Beijing 100871, China |
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| 基金项目： | Project supported by the National
Natural Science Foundation of China (Grant No 60625403), by the
Special Funds for Major State Basic Research (973) Projects and NCET
program. |
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| 摘 要： | A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.
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| 关 键 词： | 金属氧化物半导体场效应晶体管 损耗操作模式 电子学 电子管 |
| 收稿时间： | 2007-05-24 |
| 修稿时间： | 7/2/2007 12:00:00 AM |
A novel 10-nm physical gate length double-gate junction field effect transistor |
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| Hou Xiao-Yu,Huang Ru,Chen Gang,Liu Sheng,Zhang Xing,Yu Bin and Wang Yang-Yuan.A novel 10-nm physical gate length double-gate junction field effect transisto[J].Chinese Physics B,2008,17(2):685-689. |
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| Authors: | Hou Xiao-Yu Huang Ru Chen Gang Liu Sheng Zhang Xing Yu Bin and Wang Yang-Yuan |
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| Institution: | Institute of Microelectronics, Peking University, Beijing 100871, China; NASA Ames Research Center, Moffett Field, CA 94035,USA |
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| Abstract: | A novel double-gate (DG) junction field effect transistor (JFET)
with depletion operation mode is proposed in this paper. Compared
with the conventional DG MOSFET, the novel DG JFET can achieve
excellent performance with square body design, which relaxes the
requirement on silicon film thickness of DG devices. Moreover, due
to the structural symmetry, both p-type and n-type devices can be
realized on exactly the same structure, which greatly simplifies
integration. It can reduce the delay by about 60{\%} in comparison
with the conventional DG MOSFETs. |
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| Keywords: | MOSFET double-gate MOSFET depletion operation mode |
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