Reconfigurable Multiplier Blocks: Structures,Algorithm and Applications

This paper presents the efficient design methodology and applications of reconfigurable multiplier blocks (ReMB). ReMB offers significant area, delay and possibly power reduction in time-multiplexed implementation of multiple constant multiplications in many application areas from fixed digital filters, adaptive filters, and filter banks to DFT, FFT and DCT. The reader will be exposed to the fundamental principles of ReMB structures coupled with a novel algorithm for their design as well as illustrative examples where appropriate that help the reader understand the technique in action. The paper also looks into the pros and cons of deploying the technique on standard FPGA platforms as well as discussing the effectiveness of the ReMB approach in custom silicon realization by means of application examples. Area, delay and power (where possible) of the ReMB designs are compared to standard implementations. S.S. Demirsoy now with Altera European Technology Centre, High Wycombe, UK. A. Dempster now with the School of Surveying and Spatial Information Systems, University of New South Wales, Sydney, Australia.