深亚微米下芯片电源网络的设计和验证

随着芯片集成度的逐渐提高，芯片单位面积所消耗的功耗也越来越大，因此，可靠的电源网络设计和验证已成为芯片设计成败的关键因素之一。在以往。集成电路（IC）设计工程师往往根据经验来设计电源网络，但工艺到0．18um，这往往会引起芯片功能失效。根据这个问题。本文首先介绍电压降（IR-Drop）和电子迁移率（Electro-migration）现象和对芯片性能的影响；其次，提出一种有效的电源网络设计和验证方法，并在芯片的物理设计初期对电源网络作可靠性估计；最后，经过椭圆曲线加密芯片（ECC＆RSA）的流片，表明采用该方法设计的芯片，工作情况良好。

Design and Validate the Chip s Power-Network in DSM

With the dev elo pment of IC manufactur e, more and mor e t ransisto rs can be integ rated into one chip, so the consumpt ion of pow er per area becomes bigg er and bigg er. So the reliability of pow er-netw ork becomes the more important facto r in IC desig n. Before, the IC designer only based on their ex perience to design pow er- netwo rk, but w hen the process is under 0. 18 Lm, this alw ays causes the failur e o f chip. s funct ion. Accor ding to this problem, this paper discussed the reasons and the inf luences of IR-drop and EM ( Electr o-migrat ion) and int roduced a new method of designing and v alidat ing pow er-netw ork. The pow er-netw ork in the beginning o f desig ning chip w as desig ned and validated is phy sics. Finally, this metho d has been used in actual design, w hich show s it s ef f iciency .