Design of an LDO with capacitor multiplier

This paper presents a low quiescent current, highly stable low-drop out (LDO) regulator. In order to reduce capacitor value and control frequency response peak, capacitor multipliers are adopted in the compensation circuit with mathematic calculations. The phase margin is adequate when the load current is 0.1 or 150 mA. Fabricated in an XFAB 0.6 μm CMOS process, the LDO produces 12.2 mV (0.7%) overshoot voltage while the current changes at 770 mA/100 μs with a capacitor load of 10μF.