A low power 12-b 40-MS/s pipeline ADC |
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Authors: | Yin Xiumei Wei Qi Xu Lai Yang Huazhong |
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Institution: | Department of Electronic Engineering, Tsinghua University, Beijing 100084, China |
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Abstract: | This paper describes a 12-bit, 40-MS/s pipelined A/D converter (ADC) which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers (OTAs) are adopted in all pipeline stages for good power efficiency. In the first two stages,particularly, 3-bit/stage architectures are used to improve the ADC's linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate. |
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Keywords: | analog-to-digital converter A/D converter pipeline telescope OTA low power high linearity |
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