| 基于同步并行结构的视频处理IP模块的VLSI设计 |
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| 引用本文： | 张光烈,郑南宁,吴勇,张霞.基于同步并行结构的视频处理IP模块的VLSI设计[J].电子学报,2002,30(7):945-948. |
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| 作者姓名： | 张光烈 郑南宁 吴勇 张霞 |
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| 作者单位： | 西安交通大学人工智能与机器人研究所,陕西西安 710049 |
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| 基金项目： | 国家 8 63高技术超大规模集成电路SOC重大专项预启动项目 (No .863 SOC Y 2 1 ) |
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| 摘 要： | 本文在讨论隔行视频信号的逐行处理算法的VLSI实现和视频信号的色度处理和色度空间转换的硬件实现基础上,针对视频信号处理实时性,并发性以及运算量大的特点,提出了基于同步并行流水线的VLSI结构.同时结合SOC的IP模块设计给出相应的硬件实现算法.该设计已基于0.35μm CMOS工艺标准单元库进行了综合验证.
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| 关 键 词： | 同步并行结构 视频处理 IP模块 VLSI结构 |
| 文章编号： | 0372-2112(2002)07-0945-04 |
| 收稿时间： | 2001-04-24 |
VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture |
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| ZHANG Guang-lie,ZHENG Nan-ning,WU Yong,ZHANG Xia.VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture[J].Acta Electronica Sinica,2002,30(7):945-948. |
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| Authors: | ZHANG Guang-lie ZHENG Nan-ning WU Yong ZHANG Xia |
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| Institution: | Xi'an Jiaotong University,Xi'an,Shaanxi 710049,China |
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| Abstract: | This paper describes a novel design method of real time video processing,de-interlacing,color transient improvement and color space conversion,which is suitable for VLSI implementation.A synchronous and parallel pipeline architecture is proposed to reduce the complexity of video processing.The hardware design based on IP module of SOC is also discussed.This design has been verified by Synopsys EDA tool based on 0.35μm CMOS. |
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| Keywords: | synchronous and parallel architecture video processing IP module VLSI architecture |
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