高压功率集成电路中LDMOS的设计研究

高压功率集成电路(HVPIC)，是指将需要承受高电压(达数百伏)的特定功率晶体管和其它低压的控制电路部分兼容，制作在同一块IC芯片上。本文以器件模拟软件MEDICI为工具，用计算机仿真的方法，研究了一种适用于高压功率集成电路的单晶结构的LDMOS的设计问题，其中包括器件的N阱掺杂浓度、衬底浓度、P反型层浓度和结深等主要参数对击穿电压的影响，重点分析了N阱中P型反型层与漏极N^ 区距离Lp对器件耐压的影响，并分析了相应的物理意义。仿真结果表明，Lp对器件耐压有明显的影响。通过优化设计对应于各个参数器件的击穿电压变高，并且受工艺参数波动影响较小，达到了功率集成电路耐压的要求。

Research for Design LDMOS in HVPIC

HVPIC means the combination of specific power transistors that bear very high voltage (up to several hundred volts) and the control circuit biased by low voltage into a monolithic IC chip. The design problems of the single crystal LDMOS in HVPIC are analysed by means of computer simulation and on the transistor theory. The software simulation Medici is used as device simulation tool. The discussion involves N well doping concentration, substrate doping concentration, P opposite doping layer and junction depth that may affect the breakdown voltage. The author analyses influence of L_p(the space between P opposite doping layer and drain N~+ region) on the breakdown voltage. The results show that the device has a high breakdown voltage by optimum design for various parameters, and is affected slightly by the variation of process parameters.