一种改进结构的数字混频正交变换法

数字正交解调器是软件无线电（SDR）接收机的重要部件，数字混频正交变换法是实现正交解调器的常用算法。本文针对软件无线电中传统数字混频正交变换法算法，根据理论推导，提出一种适用于多频段中频信号的改进结构的数字混频正交变换法。该改进算法将正交解调与低通滤波两个过程结合在一起实现，并且每输入M个输入采样值做一次输出滤波。通过分析和在可编程器件FPGA上的实验表明，该新结构完全实现了数字混频正交变换法，且能较大地减少所占用的FPGA上的RAM和乘法器资源，在相同的FPGA资源条件下，可以较大地提高中频数字正交解调器的邻道隔离性能，或者大幅度提高所允许的前端模数采样器（ADC）的采样频率。 

An Improved Architecture for Digital Quadrature Mixing Algorithm

The digital quadrature demodulator( DQD ) is an important module in Software Defined Radio (SDR) receiver, and digital quadrature mixing algorithm is often used in the digital quadrature demodulator. In this paper, we present a reasonable improved architecture for digital quadrature mixing algorithm based on theory derivation. The improved architecture can meet the need of the multi-band intermediate frequency (IF) signal feature. In this new architecture, two courses of quadrature demodulation and low pass filtering are combined together as one module, and Low-Pass Filter (LPF) does filtering output once every M input samples. Theoretical analysis and test on programmable logic device FPGA show, the new architecture can complement digital quadrature mixing algorithm, also can apparently decrease needed RAM and multipliers of FPGA. When the FPGA resources is same, this architecture can efficiently improve adjacent channel isolation performance of mult-band IF digital quadrature demodulator, or remarkably raise sampling rate of front-end Analog Digital Convertor (ADC).