| 嫦娥一号卫星干涉成像光谱仪时序设计 |
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| 引用本文： | 邱跃洪. 嫦娥一号卫星干涉成像光谱仪时序设计[J]. 光子学报, 2009, 38(3): 495-498 |
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| 作者姓名： | 邱跃洪 |
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| 作者单位： | 中国科学院西安光学精密机械研究所,西安,710119 |
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| 基金项目： | 嫦娥一号卫星光学成像探测系统项目资助 |
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| 摘 要： | 介绍了基于Actel反熔丝FPGA的嫦娥一号卫星干涉成像光谱仪时序控制模块设计.概述了时序控制模块的功能要求,详细描述了时序控制模块外部时序接口和内部时序接口,给出了时序控制模块设计的参量配置、逻辑结构和简要结果.各项地面试验和一年的在轨飞行结果表明该设计合理可靠.
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| 关 键 词： | 嫦娥一号卫星 干涉成像光谱仪 FPGA VHDL 时序 |
| 收稿时间： | 2009-02-18 |
| 修稿时间： | 2009-04-01 |
Timing Design of the Interference Imaging Spectrometer of Chang'e-1 Satellite |
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| QIU Yue-hong. Timing Design of the Interference Imaging Spectrometer of Chang'e-1 Satellite[J]. Acta Photonica Sinica, 2009, 38(3): 495-498 |
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| Authors: | QIU Yue-hong |
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| Affiliation: | Xi'an Institute of Optics and Precision Mechanics;Chinese Academy of Science;Xi'an 710119;China |
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| Abstract: | Some information about the timing and control module design based on Actel's antifuse FPGA of the Interference Imaging Spectrometer(IIS)of Chang'e-1 Satellite was given.Functional requirements was introduced.The external timing interface and internal timing interface were discribed in detail.And,the parameter configuration,logical structure and some results were treated.Various on-ground tests and one-year on-orbit operation show that the design is reseanable and reliable. |
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| Keywords: | Chang'e-1 Satellite Interference Imaging Spectrometer FPGA VHDL Timing |
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