纳米集成电路 Cu CMP工艺模型参数优化

铜化学机械抛光受几何图形特性如线宽、间距和图形密度的影响，芯片和晶圆上铜互连线厚度的不均匀性都会影响电性能和降低良率。本文从物理化学的角度对CMP工艺进行了回顾和分析，针对Cu CMP制造工艺和在MIT提出的（Pattern-Density Step-Height，PDSH）模型基础上，建立与工艺相对应的三步骤工艺模型。为了扑捉工艺与版图结构的相关性，设计了一款65纳米测试芯片并在SMIC完成工艺实验。按照模型参数提取流程，通过芯片测试数据提取模型参数和验证工艺模型。模拟结果与测试结果对比说明二者趋势完全一致，最大偏差小于5 nm。第三方测试数据进一步证明模型参数优化取得很好的结果。精准的Cu CMP工艺模型可以用于做芯片的DFM检查、显示和消除关键热点，从而确保芯片的良率和集成电路量产能力。

Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits

A copper chemical mechanical polishing (Cu CMP) process is reviewed and analyzed from the view of chemical physics. Three steps Cu CMP process modeling is set up based on the actual process of manufacturing and pattern-density-step-height (PDSH) modeling from MIT. To catch the pattern dependency, a 65 nm testing chip is designed and processed in the foundry. Following the model parameter extraction procedure, the model parameters are extracted and verified by testing data from the 65 nm testing chip. A comparison of results between the model predictions and test data show that the former has the same trend as the latter and the largest deviation is less than 5 nm. Third party testing data gives further evidence to support the great performance of model parameter optimization. Since precise CMP process modeling is used for the design of manufacturability (DFM) checks, critical hotspots are displayed and eliminated, which will assure good yield and production capacity of IC.