HIBI Communication Network for System-on-Chip

This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates.HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μ m technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals.Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration. Erno Salminen Tampere University of Technology (TUT), Finland.Currently he is working towards his PhD degree in the Institute of Digital and Computer Systems (DCS) at TUT. His main research interests are digital systems design and communication issues in SoCs. Tero KangasTampere University of Technology (TUT), Finland.Since 1999 he has been working as a research scientist in the Institute of Digital and Computer Systems (DCS) at TUT. Currently he is working towards his PhD degree and his main research topics are system architectures and SoC design methodologies in multimedia applications. Timo D. H?m?al?ainen Tampere University of Technology (TUT), Finland. He was nominated to full professor at TUT/Institute of Digital and Computer Systems in 2001. He heads the DACI research group that focuses on three main research areas: wireless sensor networks, high-performance multi-DSP and hardware based video encoding, and design flow tools for heterogeneous MP-SoC platforms. Jouni Riihi?mki Tampere University of Technology (TUT), Finland. Currently he is working as a senior design engineer at Nokia Technlogy Platforms. He is also working towards his PhD degree. His research interests include SoC design and verification methodologies. Vesa Lahtinen received his M.Sc. and Ph.D. from TUT in 1998 and 2004, respectively. In TUT, his main research areas were system-on-chips and their interconnects. Currently, Dr. Lahtinen is a Senior Research Engineer in the Computing Architectures Laboratory of Nokia Research Center (NRC) concentrating on architecture modeling and, specifically, memory architectures. Kimmo Kuusilinna Tampere University of Technology (TUT), Finland. His main research interests include system-level design and verification, on-chip interconnections, and parallel memories. Currently he is working as a senior research engineer at the Nokia Research Center.