On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si<sub>0.45</sub>Ge<sub>0.55</sub> pMOSFETs期刊界 All Journals 搜尽天下杂志传播学术成果专业期刊搜索期刊信息化学术搜索

On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si_0.45Ge_0.55 pMOSFETs

Authors:	J. Franco B. KaczerM. Toledano-Luque Ph. J. RousselP. Hehenberger T. GrasserJ. Mitard G. Eneman L. WittersT.Y. Hoffmann G. Groeseneken

Affiliation:	^a Imec, Kapeldreef 75, 3001 Leuven, Belgium ^b ESAT, Katholieke Universiteit Leuven, Belgium ^c Dpto. Física Aplicada III, Universitad Complutense Madrid, Spain ^d Technische Universität Wien, Austria ^e FWO-Vlaanderen, Belgium

Abstract:	The negative bias temperature instability (NBTI) of nanoscaled Si_0.45Ge_0.55 pFETs with different thicknesses of the Si passivation layer (cap) is studied. Individual discharge events are detected in the measured threshold voltage shift (ΔV_th) relaxation traces, with exponentially distributed step heights. The use of a thinner Si cap is shown to reduce both the average number of charge/discharge events and the average ΔV_th step height. To qualitatively explain the experimental observations, a simple model including a defect band in the dielectric is proposed.

Keywords:	NBTI SiGe Si Cap pMOSFET Passivation Reliability
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