新型亚50纳米硅栅制作技术

提出并演示了一新型的低成本亚50纳米多晶硅栅制作技术.该技术的特点是它与光刻分辨率无关,即不需要高分辨率光刻技术.纳米尺度的栅掩膜图案是由台阶侧壁图形的转移所形成.实验结果表明,该技术制成的硅栅的栅长由形成侧壁图形的薄膜之厚度所决定,大致为该厚度的75%—85%.SEM照片显示硅栅的剖面为倒梯形结构.与其它结构(如矩形或正梯形)相比,该结构有利于减少栅电阻.

A Novel Sub-50nm Poly-Si Gate Patterning Technology

A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,i.e.,it does not contain any critical photolithographic steps.The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer.Experimental results reveal that the resultant gate length,about 75 to 85 percent of the thickness,is determined by the thickness of the film to form the spacer.From SEM photograph,the cross-section of the poly-Si gate is seen to be an inverted-trapezoid,which is useful to reduce the gate resistance.