Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors |
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| Authors: | Jae Sung Lee Jae Hwa Seo Seongjae Cho Jung-Hee Lee Shin-Won Kang Jin-Hyuk Bae Eou-Sik Cho In Man Kang |
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| Institution: | 1. School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701, Republic of Korea;2. Department of Electrical Engineering, Stanford University, CA 94305, United States;3. School of Electronics Engineering, Kyungpook National University, Daegu 702-701, Republic of Korea;4. Department of Electronics Engineering, Gachon University, 1342 SeongnamDaero, Soojung-gu, Seongnam, Kyunggi 461-701, Republic of Korea |
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| Abstract: | In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (Ion), off-current (Ioff), subthreshold swing (S), and Ion/Ioff ratio. In addition, the dependences of intrinsic delay time (τ) and radio-frequency (RF) performances including cut-off frequency (fT) and maximum oscillation frequency (fmax) on gate–drain capacitance (Cgd) with the underlapping were investigated as the gate length (Lgate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions. |
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| Keywords: | Gate-all-around (GAA) Tunneling field-effect transistor (TFET) Radio-frequency (RF) Asymmetric junctions Drain underlap |
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