| S698M SoC芯片中Cache控制器的设计与实现 |
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| 引用本文： | HUANG Lin,CHEN Di-hu,陈第虎,JIANG Xiao-hua,蒋晓华,颜军.S698M SoC芯片中Cache控制器的设计与实现[J].中国集成电路,2008,17(8). |
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| 作者姓名： | HUANG Lin CHEN Di-hu 陈第虎 JIANG Xiao-hua 蒋晓华 颜军 |
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| 作者单位： | 1. 中山大学理工学院,广东,广州,510275
2. 欧比特(珠海)软件工程有限公司,广东,珠海,519080 |
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| 摘 要： | 高速缓冲存储器Cache在微处理器中已经成为至关重要的一部分，它的使用能有效地缓和CPO和主存之间速度匹配的问题。本文以32位S698M微处理器的高速缓冲存储器Cache为例，分析了Cache的体系结构和关键技术，阐述了S698M中Cache的基本访存过程。该芯片已采用新加坡特许半导体0.18微米CMOS工艺流片成功。
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| 关 键 词： | 哈佛体系结构 直接映像 Cache一致性 指令Cache 数据Cache |
The Design and Realization of Cache Controller in S698M SoC Processor |
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| HUANG Lin,CHEN Di-hu,JIANG Xiao-hua.The Design and Realization of Cache Controller in S698M SoC Processor[J].China Integrated Circuit,2008,17(8). |
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| Authors: | HUANG Lin CHEN Di-hu JIANG Xiao-hua |
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| Abstract: | Cache is a significant part in modern microprocessor. It solves effectively the matching of speed between CPU and main memory. This paper analysis the architecture and key technology of Cache memory, describes basic access memory processing of Cache memory based on a 32-bit RISC microprocessor chip named "S698M". This SoC processor has been manufactured successfully using Chartered 0.18?mCMOS technology. |
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| Keywords: | Harvard architecture Direct-Mapped Write Through Cache coherent I-cache D-cache |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
