A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS |
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Affiliation: | 1. Department of Electronics and Communication Engineering, Indian Institute of Information Technology Guwahati, Bongora, Guwahati 781 015, India;2. Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, Guwahati 781 039, India;1. Graduate Institute of Electrical Engineering, National Taipei University, Taiwan;2. Department of Electrical Engineering, National Cheng-Kung University, Taiwan;1. Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, via Golgi 40, 20133 Milano, Italy;2. INFN, Sezione di Milano, via Celoria 16, 20133 Milano, Italy |
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Abstract: | A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm2. |
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Keywords: | SAR ADC Low power High speed Settling time Asynchronous |
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