Reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories

This study experimentally examines the reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories. Unique Schottky barrier junctions strongly enhance hot-carrier generation, ensuring high-speed multi-level programming at low gate voltages. However, strong injected gate currents might cause potential retention and endurance concerns when the programming voltage is beyond 9 V. The effective number of deep-level traps is insufficient for capturing injected electrons, such that some electrons occupy shallower states, producing retention degradation after thermal stress. The charge-trapping layers are susceptible to additional trap generation under strong gate currents, leading to considerable threshold-voltage shifts after cycling stress. A compromise of cell characteristics exists between excellent reliability and high-speed programming in 3-bit/cell Schottky barrier nanowire cells. The application of sub-8-V multi-level programming can alleviate the potential reliability generated by strong injected currents, preserving a favorable cycling endurance and thermal retention in 3-bit/cell Schottky barrier nanowire charge-trapping cells.