| CMOS电路的最大动态功耗计算和测试生成＊ |
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| 引用本文： | 金树泽,树下行三.CMOS电路的最大动态功耗计算和测试生成＊[J].电子学报,1993,21(2):48-54. |
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| 作者姓名： | 金树泽 树下行三 |
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| 作者单位： | 北方交通大学 Uniersity(金树泽)，Osaka (树下行三) |
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| 摘 要： | 本文首先提出,CMOS电路的最大动态功耗计算,可以通过计算在特定输入序列作用下电路中的不变门数的最小值来实现。本文提出的极性推导、赋值法可以快速求解不变门数的最小值,并生成相应的输入序列。该算法与电路的输入变量数无关。
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| 关 键 词： | CMOS电路 功耗计算 测试 集成电路 |
Calculation and Test Generation of the Maximum Dynamic Power Consumption lor CMOS Circuits |
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| Jin Shuze.Calculation and Test Generation of the Maximum Dynamic Power Consumption lor CMOS Circuits[J].Acta Electronica Sinica,1993,21(2):48-54. |
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| Authors: | Jin Shuze |
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| Abstract: | This paper shows that calculation of the maximum dynamic power consumption for CMOS circuits may be achieved through calculating the minimum number of non-convertion gate in the circuit with a special test sequence as input. The algorithm about polarity assignment and value assignment advanced in this paper could be used not only to solve fast the minimum number of non-convertion gate but also to generate the corresponding test sequence. This algorithm is independent of the number of input variable in the circuit. |
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| Keywords: | CMOS circuits Dynamic power consumption calculation Test generation algorithm Combinational logic circuits |
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