基于片上存储器的SDRAM换行访问低功耗设计策略

在以SDRAM为主的存储系统中,SDRAM的换行访问产生了大量的功耗开销,减少换行次数可以降低存储系统功耗。本文提出了引入片上存储器来降低SDRAM换行次数的低功耗设计策略。该策略首先对指令执行流进行分析,并统计出在对堆栈和全局变量的访问时产生了频繁换行;然后将堆栈放入片上堆栈存储器;同时借助有芯片面积约束的贪婪算法确定了片上数据存储器的大小和所存放的全局变量。实验结果表明,引入较小的片上存储器就使得换行次数大大降低,功耗显著下降,减少换行访问的功耗平均下降了24%。

Low power design of SDRAM page breaks access based on on-chip memory

The page breaks consumes a large of energy in SDARM main memory systems, as a result, the decrease of page breaks will lead to energy reduction. This paper employs the on-chip memory to reduce SDRAM page breaks access. Firstly, the instructions flow is analyzed and the results show that the access of stack and global variables contribute to high page breaks. Then, the stack data is moved into stack on-chip memory, and the size and global variables of data on-chip memory is determined by using greedy method under chip area limitation. The results show that using small on-chip memory can reduce a greate deal of page breaks and power comsumption significantly about 24% on average.