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Defect behaviors in n-channel power VDMOSFETs during HEFS and thermal post-HEFS annealing
Authors:Goran S. Risti?  Mom?ilo M. Pejovi?
Affiliation:a Faculty of Electronic Engineering, University of Niš, P.O. Box 73, 18001 Niš, Serbia and Montenegro
b National Microelectronics Research Centre (NMRC), Lee Maltings, Cork, Republic of Ireland
Abstract:The results of positive/negative Fowler-Nordheim high electric field stress and thermal post-high electric field stress annealing of commercial n-channel power VDMOSFETs have been presented. They have shown that gate bias sign has an influence on the fixed trap behavior during high electric field stress, but has no influence on any defect type behavior during thermal post-high electrical field stress annealing. In addition, slow switching traps have different behavior, but fast switching traps have the same behavior during thermal post-high electrical field stress annealing and thermal post-irradiation annealing.
Keywords:78.40.Fy   73.40.Qv   72.20.Ht   72.20.Jv
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