Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor |
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| Authors: | Zhang Xian-Jun Yang Yin-Tang Duan Bao-Xing Chai Chang-Chun Song Kun and Chen Bin |
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| Institution: | Key Laboratory of Wide Band Gap Semiconductor Materials and Devices of the Ministry of Education, School of Microelectronics, Xidian University, Xi’an 710071, China |
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| Abstract: | A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance. |
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| Keywords: | drain-induced barrier lowering effect Poisson's equation metal semiconductor field effect transistor |
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