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An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation |
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| Authors: | Yifeng Qiu Wael Badawy Robert Turney |
| Institution: | (1) Department of Electrical and Computer Engineering, University of Calgary, Alberta, Canada;(2) DSP Division, MVI Group, Xilinx Inc., Watertown, WI 53094, USA |
| Abstract: | |
| Keywords: | H 264/AVC Video codec Architecture Multi-core Accelerator Virtual socket Motion estimation DCT/Q IDCT/Q-1 CAVLC Deblocking |
| 本文献已被 SpringerLink 等数据库收录！ | |