嵌入式脉象采集仪电路设计

该脉象采集仪采用IP核技术、SoPC技术，将脉象采集的大部分功能都集成在一片FPGA内部，并自主进行了脉象采集控制的FPGA设计。该设计采用在SoPC系统外做控制电路部分，三路脉搏信号共用一个ADC，只需要很少的外部器件就能实现。与早期采用工控机、PC机，或者现在多采用的ARM设计方法相比，该脉象采集仪具有成本低，功耗低，体积小，便于扩展，稳定性高和系统维护方便等优点。

Circuit Design of Embedded Pulse Acquisition Instrument Based on SOPC Technology

This thesis is focused on the design and implementation of pulse acquisition instrument （PAI） based on SOPC technology and IP nuclear technology. A majority of the pulse acquisition functions are integrated into a piece of FPGA, and the FPGA design of pulse acquisition control is performed autonomously, the control circuit is used outside the SOPC system, the same ADC is shared by three-way pulse signal, and few external devices are needed. Compared with the design methods of early industrial PC, PC or current ARM system, the PAI design has some advantages, such as low-cost, low power consump tion, small size, easy to expand and to use, high stability and reliability, etc.