A data optimization test technique for characterizing embedded ADCs

A novel data optimization test technique is presented which utilizes a BIST structure, an ADC model and histogram data to characterize embedded ADCs. A practical 8 bit ADC is modeled and then characterized using 20% less data points then conventional analysis with a 78% reduction in the amount of data required to be shifted off-chip. Comparisons between theoretical, modeled and practical results are also made in the paper.