首页 | 本学科首页   官方微博 | 高级检索  
     检索      

基于FPGA的高速加密芯片的设计与实现
引用本文:杨卫国,张涛,袁宏韬,闫景富.基于FPGA的高速加密芯片的设计与实现[J].吉林大学学报(信息科学版),2005,23(6):595-600.
作者姓名:杨卫国  张涛  袁宏韬  闫景富
作者单位:中国科学院,长春光学精密机械与物理研究所,长春,130022;中国科学院,声学研究所,北京,100080
摘    要:以非线性组合函数和线性反馈移位寄存器(LFSR:Linear Feedback Shift Registers)为基础,利用可编程逻辑门阵列(FPGA:Field-Programmable Gate Array)设计了一个高速加密芯片.该芯片既能满足密码学领域对密钥序列的高质量要求,又能满足保密通信领域高速度要求.介绍了加密芯片的设计理论、设计过程、加密芯片安全性分析和硬件实现,最后对密钥流进行了随机性统计测试.

关 键 词:非线性组合函数  加密芯片  伪随机序列  可编程逻辑门阵列
文章编号:1671-5896(2005)06-0595-06
修稿时间:2004年12月25日

Design and Implementation on High-Performance Encryption Chip Based on FPGA
YANG Wei-guo,ZHANG Tao,YUAN Hong-tao,YAN Jing-fu.Design and Implementation on High-Performance Encryption Chip Based on FPGA[J].Journal of Jilin University:Information Sci Ed,2005,23(6):595-600.
Authors:YANG Wei-guo  ZHANG Tao  YUAN Hong-tao  YAN Jing-fu
Abstract:A high-performance encryption chip which is based on LFSR(Linear Feedback Shift Registers),nonlinear combining functions and FPGA(Field-Programmable Gate Array) has been designed,which can be used in the cryptography field.In addition,it can also be applied in the encryption communications field.Firstly,the design principles and process of the encryption chip were narrated.Secondly,a encryption chip has been designed.Finally,the article gives the randomicity testing result of encryption sequence according to the special standard.
Keywords:nonlinear combining functions  encryption chip  pseudo-random sequence  field-programmable gate array(FPGA)
本文献已被 CNKI 维普 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号